1. Field of the Invention
The present invention relates to a mounting structure for semiconductor devices, more particularly relates to a mounting structure for semiconductor devices for mounting a plurality of semiconductor devices stacked together.
2. Description of the Related Art
One method of mounting semiconductor devices on a mounting substrate is to mount a plurality of semiconductor devices stacked on each other. This mounting method has the advantages of enabling semiconductor devices to be efficiently mounted in a set planar region and enabling the length of the interconnection patterns to be shortened compared with the case of arranging semiconductor devices planarly and therefore enabling the increasing speed of signals to be handled. Recently, extremely thin semiconductor chips of several tens of pm to 200 xcexcm have been provided. Therefore, the method of mounting semiconductor devices stacked on each other is effective from the viewpoint of enabling application even to products limited in thickness.
FIG. 8 is an explanatory view of an ordinary mounting method for mounting semiconductor devices 10 stacked on each other. In the FIG. 11 represents a semiconductor chip 12 a substrate on which a semiconductor chip 11 is placed, 14 a connection terminal formed in a bump shape for bonding substrates 12 stacked together, and 15 a mounting substrate. In the illustrated example, each semiconductor chip 11 is bonded to a substrate 12 by an anistropic conductive adhesive 16 and is electrically connected to first ends of interconnection patterns 20 formed on the surface of the substrate 12 through gold bumps 18. The connection terminals 14 are electrically connected to the second ends of the interconnection patterns 20 formed on the substrate 12 and are electrically connected to interconnection patterns 20 of an adjoining substrate 12 through connection holes 22 formed in the substrate in register with the positions of arrangement of the connection terminals 14.
Summarizing the problem to be solved the invention, when stacking semiconductor devices 10 carrying semiconductor chips 11 on substrates 12, normally, as shown in FIG. 8, the planar arrangements of the connection terminals 14 of the stacked semiconductor devices 10 are made the same and connection terminals 14 are designed to project vertically from the mounting surface of the mounting substrate 15 when the semiconductor devices 10 are stacked.
When making the planar arrangement of the connection terminals 14 of each layer the same and stacking semiconductor devices 10 so that the connection terminals 14 project out as completely straight columns, stress easily concentrates at the connection terminals 14 and the reliability of the bonds between the mounting substrate 15 and connection terminals 14 falls.
The problem of the deterioration of the reliability of the bonds between the mounting substrate 15 and the connection terminals 14 arises due to the difference in the heat expansion coefficients of the mounting substrate 15 and semiconductor devices 10 (semiconductor chips 11, substrates 12, and anistropic conductive adhesive 16). When stacking semiconductor devices in multiple layers, reducing the stress concentration at the bonds of the mounting substrate and the connection terminals and the stress concentration between the mounting substrate and the semiconductor devices as much as possible becomes important in improving the reliability of the finished product.
An object of the present invention is to solve the problem when mounting semiconductor devices stacked on a mounting substrate and provide a mounting structure for semiconductor devices of a high reliability which eases the stress concentration occurring between the mounting substrate and the connection pads of the semiconductor devices when mounting semiconductor devices stacked together.
To achieve this object, the present invention provides a mounting structure for semiconductor devices wherein a plurality of semiconductor devices each comprised of a semiconductor chip carried on a substrate and provided with connection terminals formed in bump shapes on the substrate are stacked in multiple layers in the vertical direction and mounted on a mounting substrate by electrically connecting the adjoining semiconductor devices through the connection terminals, wherein the connection terminals of the adjoining semiconductor devices are arranged to overlap each other and the connection terminals of the adjoining semiconductor devices are arranged to be displaced from each other in planar arrangement.
In one preferred embodiment, the connection terminals are arranged successively displaced inside from the semiconductor device of the bottommost layer mounted on the mounting substrate to the semiconductor device of the topmost layer.
In another preferred embodiment, the connection terminals are arranged successively displaced outside from the semiconductor device of the bottommost layer mounted on the mounting substrate to the semiconductor device of the topmost layer.
In still another preferred embodiment, the connection terminals are arranged inside and outside from the semiconductor device of the bottommost layer mounted on the mounting substrate to the semiconductor device of the topmost layer.
In still another preferred embodiment, the semiconductor chips and connection terminals are arranged on the same surface of the substrate.
In still another preferred embodiment, the semiconductor chips and connection terminals are arranged on opposite surfaces of the substrate.
In the above preferred embodiments, each of the semiconductor device is formed with interconnection patterns on one surface of its substrate and connection terminals of the adjoining semiconductor devices are electrically connected with the interconnection patterns through connection holes formed passing through the substrates.